In a transceiver, such as a serializer/deserializer (SERDES), a clock delivery system can include a phase-locked loop (PLL) that generates one or more dock signals for use in transmitting and receiving data. A phase interpolator (PI) can be used to interpolate a clock signal by shifting its phase by a discrete amount over a given range. For example, a PI can shift the phase in steps that are a fraction of a unit interval (UI), such as 1/64 UI. In a transmitter, a PI is used to adjust the phase the phase of the transmitted data. In a receiver, a PI is used to adjust the phase of the sampling clock used to sample the received data.
Various applications that use a SERDES may assume that the spacing between phase steps of a PI (“phase distribution”) is uniform. Thus, non-linear phase distribution of a PI will affect the precision of the application being supported. Non-linear phase distribution is caused by silicon impairments and thus each SERDES can have different non-linear phase distributions for different instances of PIs therein. Many applications would benefit from knowing the specific phase distribution(s) of the specific SERDES being used. While the phase distribution of a PI can be determined using an external high-speed scope, such testing is limited to a laboratory environment and becomes impracticable at production level.